Via structures (e.g., interconnect structures) are a critical component of semiconductor devices. For example, via structures are used to interconnect wiring structures on different layers of the device. The via structures are formed by complex fabrication processes, e.g., lithography, etching, deposition and planarization processes, which are costly and time consuming.
More specifically, after a deposition of interlevel dielectric material over a lower wiring layer, lithography and etching processes require deposition of several different hardmask layers and resist formation, followed by exposure of energy through complex masking processes. After each of the etching processes, the material needs to be removed. Once a trench or via is formed in the interlevel dielectric layer, a metal deposition process is required to form the via structures. The deposition process, though, leaves a residue of metal material on the interlevel dielectric material, requiring additional processing steps, e.g., including a chemical mechanical polishing (CMP) process. In addition, as technology nodes continue to scale downwards, the fabrication processes become ever more complex and costly.